1. Technical Field
Embodiments of the present invention relates to a semiconductor memory apparatus, and in particular, to a technology for transmitting data to a memory cell.
2. Related Art
A dynamic random access memory (DRAM) among semiconductor memory apparatuses is a typical volatile memory. A memory cell of the DRAM includes a cell transistor and a cell capacitor. The cell transistor plays a role of controlling an access to the cell capacitor and the cell capacitor plays a role of storing charges corresponding to data. In other words, the data are classified into a high-level data or a low-level data according to the charge amount stored in the cell capacitor.
Meanwhile, the charges are input and output to and from the cell capacitor using a leakage component and thus, the memory cell of the DRAM should periodically store the corresponding data. As described above, a periodically performed operation in order to accurately maintain the data is referred to as a refresh operation.
The memory cell of the DRAM is activated in an active mode and the bit-line sense amplifying circuit senses and amplifies data transmitted from the activated memory cell and transmits them to the memory cell again. In addition, the memory cell is deactivated in the precharge mode to maintain the data. In other words, it can be said that the refresh operation repeatedly performs the active operation and the precharge operation at a predetermined period.
Meanwhile, when the leakage component is increased, a data retention time for the memory cell to reliably maintain the data after the precharge operation becomes short and thus, a technology to improve this has been needed.